In general, a Schottky diode is a device using a metal-semiconductor junction. The Schottky diode has excellent high-speed switching characteristics compared to a general PN junction diode. The reason is that when a forward voltage is applied to the Schottky diode, there is no RC delay caused by minority carrier injection (MCI) which may occur in the PN junction.
Generally, a diode should have low forward voltage drop characteristics and low leakage current characteristics to meet the trend toward high power and high speed operation. The Schottky diode strongly exhibits these characteristics compared to the PN junction diode.
The Schottky diode must improve reverse characteristics (e.g., reverse voltage and leakage current) to withstand high voltages and high temperatures. Also, the Schottky diode must enhance forward characteristics (turn-on resistance (Ron) characteristics) to be capable of rectifying high-density current. However, since there is a trade-off relationship between forward characteristics and reverse characteristics, careful engineering is required to take all characteristics in account.
FIGS. 1A to 1F illustrate cross-sectional views showing the steps of a related method for fabricating a Schottky diode using a CMOS process. As shown in FIG. 1A, a P-type oxide film 2 is grown over the surface of a P-type silicon substrate 1. Then, a first photoresist film 3 is deposited and patterned by a photolithography process to define an N-well formation region. Then, an ion implantation process for implanting N-type impurities is performed using high voltage and low voltage N-well masks.
As shown in FIG. 1B, a diffusion process forms an N-type impurity diffusion region 4. When the density of high voltage N-well impurities is low, the breakdown voltage increases, but the forward conducting resistance also increases, thereby reducing the current carrying capacity.
As shown in FIG. 1C, a pad oxide film or a pad nitride film 5 is formed over the entire surface of the P-type silicon substrate 1 including the N-type impurity diffusion region 4. Then, a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process forms a device isolation film 6. The device isolation film 6 may be formed of a silicon oxide film. For example, the P-type silicon substrate 1 with the pad nitride film 5 is patterned using a device isolation mask, and a photolithography process using an N-type field mask is performed. Then, boron (B) ions for edge termination are implanted at the edges of an active region of anode and cathode formation regions. A thermal oxidation process is performed to form the device isolation film 6. Then, the residual pad nitride film 5 may be removed.
As shown in FIG. 1D, a second photoresist film is formed and patterned to expose a cathode formation region 7. Then, a lightly doped impurity region 7 or a lightly doped drain (LDD) is formed in the cathode formation region 7 using an N-type mask.
The second photoresist film is removed and a third photoresist film 9 is formed and patterned to expose an anode formation region 8. Then, a lightly doped impurity region 8 or a lightly doped drain (LDD) is formed in the anode formation region using a P-type mask. In other words, a photolithography process using N-type and P-type masks and an ion implantation process are performed to form an N-type junction 7 in the cathode formation region and a P-type junction 8 in the anode formation region. The N-type and P-type junctions 7 and 8 are formed to provide an ohmic contact.
As shown in FIG. 1E, a fourth photoresist film 13 is formed and patterned to expose the cathode formation region. Further, an ion implantation process of N+ impurities is performed in the cathode formation region to form an N+ impurity diffusion region 10.
As shown in FIG. 1F, the fourth photoresist film 13 is removed and a fifth photoresist film is formed and patterned to expose the anode formation region. P+ impurities are implanted in the anode formation region to form a P+ impurity diffusion region 11 and 12. Then, an interlayer insulating film 15 is formed over the entire structure, and a photolithography process using a contact mask is performed to expose the cathode and anode formation regions.
A Ti film serving as Schottky barrier metal is deposited over the entire structure and rapid thermal treatment is performed to form a Ti silicide film 17 over the surface of the anode and cathode formation regions. A TiW film 16 serving as Schottky barrier metal is deposited, and an Al film 14 serving as interconnection metal is deposited thereon. A photolithography process using an electrode mask and an etching process are performed on the Al film 14 to define an anode electrode and a cathode electrode, and thermal treatment is performed on the Al film 14.
In the related Schottky diode described above, as shown in FIG. 2, there is a problem of forming a parasitic PN junction diode (“PN-Diode” in FIG. 2) by the N-type impurity diffusion region 4 formed over the P-type silicon substrate 1. Specifically, when a negative voltage or ground voltage is applied to the cathode of the Schottky diode (“S-Diode” in FIG. 2) while the P-type silicon substrate 1 having the Schottky diode is grounded, a parasitic PN junction diode is formed between the P-type silicon substrate 1 and the N-type impurity diffusion region 4. Accordingly, the related Schottky diode may malfunction in the circuit by the operation of the parasitic PN junction diode.